During conventional semiconductor manufacturing processes, numerous coatings are applied to and removed from semiconductor wafers. In one typical process, a layer of spin-on glass (SOG) is applied over the semiconductor wafer. The SOG is comprised of a low viscosity, highly carbonated SiO.sub.X compound in an alcohol carrier. The SOG is most frequently applied to improve the planarity of the layers deposited over the semiconductor wafer. That is, the SOG is a non-conformal substance which fills gaps, holes, or crevices in the underlying layers. Commonly, a desired amount of SOG is applied to the top upwardly-facing surface of the semiconductor wafer while the semiconductor wafer is being rotated. Thus, as the semiconductor wafer is rotated, the SOG spreads radially outward from the center of the semiconductor wafer towards the edge of the semiconductor wafer such that the entire top or active surface of the wafer is coated with a layer of SOG. The thickness of the SOG layer depends on the topography underlying the SOG layer.
Prior Art FIG. 1A, illustrates a prior art semiconductor manufacturing process step in schematic cross-section. As shown in Prior Art FIG. 1A, a semiconductor wafer 10 has metal lines 12 and 14, and an oxide film formed from tetraethylorthosilicate (TEOS) layer 16 disposed thereon. After highly conformal (i.e. uniform thickness independent of topography) TEOS layer 16 is deposited over metal lines 12 and 14 the topography above semiconductor wafer 10 is not planar. Specifically, gaps, holes, or crevices, shown in region 18, create an undesirable surface topography.
With reference next to Prior Art FIG. 1B, a non-conformal SOG layer 20 is shown deposited over TEOS layer 16. SOG layer 20 significantly planarizes the topography above semiconductor wafer 10. That is, SOG layer 20 reduces the severity or depth of the gap in region 18. As shown in Prior Art FIG. 1B, a slight depression still exists in region 18 even after the deposition of SOG layer 20.
As shown in Prior Art FIG. 1C, after the deposition of SOG layer 20, SOG is subjected to an etching process or "etchback". The etchback reduces the thickness of SOG layer 20. In Prior Art FIG. 1C, SOG layer 20 has been etched until it is relatively even with the exposed portion of TEOS layer 16 disposed on top of metal lines 12 and 14. As shown in Prior Art FIG. 1C, a slight gap still exists in region 18 after etching of SOG layer 20. To ensure that no SOG exists in subsequent vias for electrical connections to metal lines 12 and 14, SOG layer 20 and at least part but not all of the exposed portion of TEOS layer 16 must be removed from the top of metal lines 12 and 14. Thus, the exposed portion of TEOS layer 16 disposed on top of metal lines 12 and 14 will be partially removed. However, during the portion of the etch process when TEOS layer 16 is exposed, SOG layer 20 will also be etched in order to maintain a substantially planar topography above semiconductor wafer 10. In the prior art, etchback of SOG layer 20 and TEOS layer 16 is commonly performed in a fluorine- based reactive ion etching environment. As an example, a common fluorine-based compound is a mixture of freon 23 (CHF.sub.3) and freon 14 (CF.sub.4).
Referring now to Prior Art FIG. 1D, a side sectional view is shown. Prior Art FIG. 1D shows the topography of SOG layer 20 after the exposed portion of TEOS layer 16 has been partially etched from the top of metal lines 12 and 14. As illustrated by Prior Art FIG. 1D, the etching of the exposed portion of TEOS layer 16 from the top of metal lines 12 and 14 accelerates the etching rate of nearby SOG layer 20. That is, in region 18, SOG layer 20 is etched much more rapidly than the exposed portion of TEOS layer 16 was etched from the top of metal lines 12 and 14 because of the interaction of the TEOS layer 16 in the plasma. More specifically, the etch rate of SOG layer 20 is accelerated by the exposure of TEOS layer 16. As a result of the increased etch selectivity, the gap in region 18 deepens or becomes more severe. Thus, the gap-filling properties of SOG layer 20 are compromised. While such gaps may be tolerable in 0.8 micron-based processes, such gaps are not generally acceptable for 0.35 micron-based and tighter intermetal spacing processes due to interactions with subsequent layer processing which generates fatal defects.
The increased selectivity and "etchback" rate of SOG layer 20 near the etched portion of TEOS layer 16 is due to localized oxygen microloading. That is, when an oxygen-rich layer such as TEOS layer 16 is etched, oxygen is released into the plasma. Portions of SOG layer 20 located near the released oxygen adsorb the released oxygen. Such a process "loads" that portion of SOG layer 20 with oxygen. The oxygen reacts with carbon in SOG layer 20, forms carbon monoxide, and accelerates the rate at which SOG layer 20 is etched in region 18. In addition to deleteriously accelerating the local etchback rate of SOG layer 20, oxygen microloading also globally accelerates the SOG etch rate across the wafer. The etch rate dependence of SOG on oxygen exaggerates other more subtle process parameters such as SOG coat thickness and compositional variations.
As a further disadvantage, oxygen microloading inhibits empirically obtaining a reliable SOG/TEOS etch rate ratio. That is, in order to calculate or predict an SOG/TEOS etch rate ratio on a product wafer, the etch rate of SOG and TEOS are individually determined on flat, blanket wafers. However, when determining the etch rate for a blanket layer of SOG, it is extremely difficult to quantitatively determine factors such as oxygen microloading. Thus, the etch rate observed for an SOG layer by itself, does not necessarily reflect the actual etch rate of the SOG layer when it is etched concurrently with a TEOS layer. Likewise, the etch rate observed for a blanket layer of TEOS, does not necessarily reflect the actual product etch rate of TEOS when etched concurrently with SOG. Thus, the predicted ratio of SOG etchback to TEOS etchback, does not accurately reflect an actual SOG/TEOS etch rate ratio or selectivity. As a result, etch parameters based upon the predicted SOG/TEOS etch rate ratio do not always provide a predictable result. As shown in Prior Art FIG. 1D, etch parameters based upon a predicted SOG/TEOS etch rate ratio, result in deepening the gap in region 18. The etch unpredictability consequently results in reduced process margin and latitude.
With reference again to Prior Art FIG. 1C, once SOG layer 20 is deposited over TEOS layer 16, SOG layer 20 significantly planarizes the topography above semiconductor wafer 10. That is, after the deposition of SOG layer 20, only a slight gap remains in region 18. However, as shown in Prior Art FIG. 1D, etching of SOG layer 20 can degrade the planarity instead of improving the planarity as desired.
Thus, the need has arisen for a method which reduces or prevents oxygen microloading of an SOG layer, a method which achieves controlled etchback by generating a reliable SOG/TEOS etch rate ratio less dependent on the amount of oxygen in the plasma, and a method which achieves planarity on a semiconductor substrate.